3D00900 - SEMI 3D9 - Guide for Describing Materials Properties for a 300 mm 3DS-IC Wafer Stack StdPbc-1114 stacked chip on substrate (SCoS)

stacked chip on substrate (SCoS)

the Sensor/Actuator Network Common Device Model

but not part of the requirements) on the 200 mm wafer size

This Standard covers specifications for services to and events from CLJ and CFJ models

3D00900 - SEMI 3D9 - Guide for Describing Materials Properties for a 300 mm 3DS-IC Wafer Stack StdPbc-1114 stacked chip on substrate (SCoS)1 Purpose 1. 1 This Guide is intended to address the needs of the 3D Stacked IC (3DS IC) industry by providing the tools needed to procure wafer stacks to be used in a 3DS IC process. 2 Scope 2. 1 This Guide provides the tools to describe wafer stacks in a 3DS IC process. A wafer stacking process takes two or more intermediate wafers and forms a stack, which can then be further processed as if it were a single wafer. After bonding the dimensions of